1. Field of the Invention
The invention relates to a semiconductor memory device having a multiplicity of memory cells disposed on a semiconductor substrate, each of the memory cells has a selection transistor disposed in a plane extending substantially parallel to the surface of the semiconductor substrate, each selection transistor has a gate terminal, a first electrode terminal and a second electrode terminal, each of the memory cells has a storage capacitor associated with and triggerable by the selection transistor, the storage capacitor has a ferroelectric dielectric, a first capacitor electrode and a second capacitor electrode, each gate terminal of the selection transistor is connected to a word line of the semiconductor memory device, each first electrode terminal of the selection transistor is connected to a bit line, and each first capacitor electrode of the storage capacitor is connected to a common conductor layer of electrically conductive material. The invention also relates to a method for producing such a semiconductor memory device. Such a semiconductor memory device having a storage capacitor with a ferroelectric dielectric (a so-called FRAM) is known, for instance, from The 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 55 ff. by R. Moazzami et al, and from The 1994 IEEE International Solid-State Circuits Conference, pp. 268 ff. by Tatsumi Sumi et al. In that semiconductor memory device the storage capacitors with the ferroelectric dielectric are constructed in planar fashion and because of the wiring the also have cell surface areas of considerable size per bit, which is considered to be disadvantageous in view of the desired large scale of integration. Despite the problems that so far still exist, a great future is predicted for ferroelectric memories or FRAMs. They could entirely replace present semiconductor memories (DRAMs, SRAMs, EEPROMs, flash EEPROMs). The advantage of FRAMs resides above all in the brief programming time (&gt;20 ns), a low programming voltage (from about 3 V of supply voltage to the ICs), low energy consumption in programming (no charge pump required), and frequent programmability (10.sup.12 demonstrated and 10.sup.15 expected, compared with 10.sup.5 in EEPROMs). Examples of materials for the ferroelectric layer that appear especially promising at present are lead zirconium titanate, strontium tantalate, or compounds thereof. One of the problems that are still an obstacle to rapid introduction of FRAM technology is an as-yet unsolved compatibility with a production process for integrated circuits. In particular, a necessity for platinum electrodes in the ferroelectric storage capacitor and a spin-on coating, which heretofore has been conventional, for applying a ferroelectric gel, which is associated with a relatively great layer thickness and thus a capacitance that requires a large surface area, heretofore prevented profitable use in semiconductor technology, so that heretofore no process for producing FRAMs that is suitable for mass production was known. In this respect it must also be remembered that depositing the relatively complex materials for the ferroelectric dielectric, a problem of a satisfactory source which is suitable for the process that is associated therewith, and moreover a lack of quality of the layers because of fissuring, leakage currents, temperature influences and electrode adhesion, all contribute to the problems of process integration. In particular, the ferroelectric materials known heretofore react especially sensitively to hydrogen. However, hydrogen can hardly be suppressed in the known methods for producing a semiconductor memory device, and in such methods occurs especially in plasma deposition processes and plasma etching processes. In addition to those FRAM cells, large-scale integration DRAM semiconductor memories with conventional materials for the storage capacitor dielectric are known. In order to make DRAM semiconductor memories with a memory capacity of up to about 256 MB at present, dielectrics with a high dielectric constant are used so that as the cell area becomes smaller an adequate capacitance, typically of more than about 20 fF per cell, is still attainable. Heretofore, for those purposes, an ONO layer has been used in most cases, but its technological limits have become apparent in the meantime, since upon a further reduction in thickness the leakage current rises above the predetermined limit value, and adequate capacitances (surface areas) can be obtained only through the use of such complicated structures as trench or stacked capacitors. For those reasons, new materials that have a high enough dielectric constant are therefore increasingly being used for the dielectric of the storage capacitor. However, the alternative dielectric materials known thus far are extremely sensitive to the usual strains arising in the method used heretofore to produce a semiconductor memory device, namely stability to high process temperatures, undesired chemical reactions, and the like.